Hardware / Software Co-Design Using Simulink
Fig1: High-level to hardware implementation flow
High level development requires a language, graphical or text-based, with which a developer can describe an algorithm or system using blocks a high level of abstraction. The level of abstraction of the language is such that the developer connects blocks with complex functionality and concerns himself mostly with the design aspect and not so much with lower level details. Simulink provides the interface to accomplish the design and simulation of the system. Simulink also has the capability of compiling to software (Simulink Embedded Coder) or to HDL (Simulink HDL Coder) but not to both simultaneously. Because embedded systems platforms tend not to be standardized in choice of FPGAs (field programmable gate array), CPUs, DSPs (digital signal processor) and the buses that connect these components, Simulink does not provide the high level interfaces to connect these components. High-level design is useful as an academic exercise and is reinforced when the synthesized design can be brought into the real-world. Through the use of MATLAB scripts to analyze a Simulink model produced by the developer and Python scripts to generate HDL and insert HDL components into the top level design, a nearly automatic flow will be possible from the high-level model to CPU and FPGA binaries.
Fig 2: Personal Active Learning Platform (PAL):
TLL6527M from The Learning Labs
The platform that runs the synthesized system is the TLL PAL (Personal Active Learning). The goal of this project is to design an interface between the EBIU (external bus interface unit) of a Blackfin BF527 DSP and a Xilinx Spartan 3E 500K FPGA. The EBIU supports a 16-bit data bus with access controlled by the DSP. The software portion of the design is nearly plug and play due to libraries that implement EBIU access. The FPGA interface (called a proxy) handles data intake, temporary storage and application control (so that the application is only enabled once data has been received on all ports) and data output once the application is ready to present data to the DSP. Through the use of the hardware and software proxies, development on the top-level becomes more feasible for system level designers.
The benefit of designing a system that uses a processor and an FPGA is realized when the FPGA implements an algorithm without the overhead of instruction decoding and can often complete the work of several CPU cycles in 1 cycle using parallelism.